But I obviously encounter problems since I'm probably still thinking a bit too much software programming I guess.The problem I have is that the counter increases to 1 right away when it enters the process so that when I try to add the vectors a = 0101 0101 and b = 1010 1010 I get y = 1111 111X and the carrys = 0000 000X. The logic behind it is very easily understood, you just have a counter for the index and so on. I'm trying to implement a serial adder/subtractor in VHDL, I've done it the ripple carry way before but now I'm supposed to implement the same functionality by just using one full adder cell instead of N-amount of cells so I have to shift the bits from the vectors in to the full adder/subtractor and store the result in another vector which I just shift the index for as well.

Serial Adder With Accumulator Verilog Code Serial Adder With Accumulator Verilog Code.ALL entity SAVHDL is Port ( I: in stdlogicvector ( 15 downto 0 ) O: out stdlogicvector ( 7 downto 0 ) ci, ai, bi, co, so: out stdlogic CLK: in stdlogic Load: in stdlogic ) end SAVHDL architecture Behavioral of SAVHDL is signal ina, inb, oreg: stdlogicvector ( 7 downto 0 ) signal so, ci, co: stdlogic begin -rec ina process ( CLK ) begin if CLK 'event and CLK = '1' then if ( Load = '1' ) then ina.

Verilog code for serial adder verilog